The present invention applies to non-reprogrammable logic devices. More particularly, this invention relates to methods of optimizing logic in non-reprogrammable logic devices.
Programmable logic devices (PLDs) are well known. Early programmable logic devices were one-time configurable. For example, configuration may have been achieved in a laser programmable device, for instance, by “burning”—i.e., opening—fusible links. Alternatively, the configuration may have been stored in a programmable read-only memory. These devices generally provided a user with the ability to configure the devices for “sum-of-products” (or “P-TERM”) logic operations. Later, such programmable logic devices incorporated erasable programmable read-only memory (EPROM) for configuration became available, allowing the devices to be reconfigured.
Still later, programmable logic devices incorporating static random access memory (SRAM) elements for configuration became available. These devices, which can also be reconfigured, store their configuration information in a nonvolatile memory such as an EPROM, from which the configuration is loaded into the SRAM elements when the device is powered up. These devices generally provide the user with the ability to configure the devices for look-up table-type logic operations. At some point, such devices began to be provided with embedded blocks of random access memory that could be configured by the user to act as random access memory, read-only memory, or logic (such as P-TERM logic).
In all of the foregoing programmable logic devices, both the logic functions of particular logic resources in the device, and the interconnect resources for routing of signals between the logic resources, were programmable. Alternatively, non-reprogrammable or one-time programmable devices such as mask-programmable logic devices (MPLDs) have been provided. With mask-programmable logic devices, instead of selling all users the same device, a manufacturer produces a base device that depends on a user's specifications and that is not programmable by the user.
Specifically, the user provides the manufacturer of the mask-programmable logic device with the specifications of a desired device, which may be the configuration file for programming a comparable conventional programmable logic device (“source PLD”). The manufacturer then uses that information to program the logic functions of the base device and also to configure the routing of the device. Thus, unlike in a programmable logic device, where the same programmable interconnect resources are in every device, in a mask-programmable logic device the routing is configured by the manufacturer based on the user's specifications and can inevitably vary from device to device.
In addition, the logic resources for conventional programmable logic devices often contain generic look-up tables (LUTs) that allow the user to implement a desired logic function. However, as a result, these devices invariably include resources that are unoptimized or that may not be used for a particular design.
Accordingly, it would be desirable to provide a method for optimizing the area, performance, and power consumption of a non-reprogrammable logic device that implements a pre-existing circuit design by reducing the number of gates and logic levels needed to implement logic functions in such devices.